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EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
JANUARY 2009 REV. 1.05
FEATURES GENERAL FEATURES
* Six independent 3/1.5Gbps SATA ports. * Connects 2 host ports to 4 device ports. * Supports 3/1.5Gbps rate detection/speed
negotiation.
independent hosts, the XRS10L240 offers a leading solution for propagation of high data rate Serial ATA products in a wide variety of applications. The integration of Serial ATA PHY links, a variety of digital logic capabilities, rate adjust FIFOs, integrated lowcost clock oscillator support, test and loopback features is achieved in a low cost and lower power implementation. The port selector function is used when dual hosts, such as I/O controllers, must access single-port disk drives in high availability storage subsystems where redundancy and load sharing are important. The outputs from the I/O controllers are multiplexed to a Serial ATA drive through the port selector block of the XRS10L240. Active/passive port selector in XRS10L240 allows two different host ports to connect to the same target in order to create a redundant path to that target. In combination with RAID, the XRS10L240 allows system providers to build fully redundant solutions. This avoids the presence of a single point of failure, and enables a fail-over path in the case of host failure. This port multiplier function is used when one active host has to communicate with multiple SATA drives. The XRS10L240 supports up to 4 SATA drives and utilizes the full bandwidth of the host connection. The XRS10L240 includes enhanced features such as staggered HDD spin-up, power management control, hot plug capability and support for legacy software. The XRS10L240 acts as a retimer, maintaining independent signaling domains between the drives, hosts and the external interconnect. The high-speed serial input feature: selectable equalization and the high-speed serial output feature: programmalbe pre-emphasis can be used to compensate for ISI (Inter-Symbol Interference) and increase maximum cabling distances. XRS10L240 meets tight jitter budgets in SATA applications. Exar's serial I/O technology enables reliable data transmission over 1 meter or more of FR-4 and 4 meters or more of unequalized copper cable. Host and drive port speeds can be mixed and matched, based upon inherent data rate negotiation present in the SATA II specifications. The MDIO bus allows simple configuration of the XRS10L240 when needed. Receive equalization, transmit amplitude and pre-emphasis and SSC control are all configurable via the 2-wire MDIO interface.
* Supports power down modes - Active, partial,
slumber and power down.
* Advanced features configurable through MDIO
bus. PORT MULTIPLIER/SELECTOR LOGIC FEATURES
* Low latency architecture. * Supports OOB signaling for SATA applications.
Internal OOB detectors COMINIT and COMWAKE. I/O FEATURES for COMRESET/
* High speed outputs with programmable preemphasis to drive long interconnects.
* Selectable high speed input equalization for
optimum reception.
* Compliant with SATA Gen-2i & Gen-2m
specification.
* Enables reliable data transmission over 1 meter
or more of FR-4 and 4 meters or more of unequalized copper cable.
* Selectable spread spectrum clocking (SSC) to
reduce EMI. PHYSICAL FEATURES
* CMOS 0.13 Micron Technology * Single 1.2 V Power Supply * -40C to 85C Industrial Temperature Range * No heatsink or airflow required * 100-Pin LQFP Package
1.0
INTRODUCTION
The XRS10L240 provides the combined advantages of the Serial ATA II Port Selector and Port Multiplier implementations for Serial ATA II systems at 3.0 Gbps and 1.5 Gbps. Combining the capability to address four Serial ATA devices from one external link with support for a failover path from two
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
REV. 1.05
To summarize, the port multiplier functionality in the XRS10L240 allows the system designer to increase the number of serial ATA connections in an enclosure that does not have a sufficient number of serial ATA connections for all of the drives in the enclosure. The port selector functionality in the XRS10L240 allows replacement for expensive Fibre Channel drives with cost effective and high capacity SATA drives in enterprise class applications without compromising on redundancy or performance. STANDARDS COMPLIANCE The XRS10L240 is compliant with the following industry specifications:
* Serial ATA, Revision 1.0a * Serial ATA II: Extensions to Serial ATA 1.0a, Revision 1.2 * Serial ATA II PHY Electrical Specifications, Revision 1.0 * Serial ATA II: Port Selector, Revision 1.0 * Serial ATA II: Port Multiplier, Revision 1.2 * Serial ATA II: Revision 2.6
APPLICATIONS
* Serial ATA Enclosures * Other Serial ATA link replicator applications * Buffers for externally connected links * High density storage boxes * RAID Subsystems
APPLICATION EXAMPLE The XRS10L240 is ideally suited for use within an external drive enclosure as a means of providing redundant host access to ensure system availability and reliability, while enabling access to up to four target devices per XRS10L240. This application is shown in Figure 1. Other applications for the XRS10L240 include use in fixedcontent or network attached storage systems, storage arrays, desktop applications or entry-level servers, RAID storage or disk-to-disk backup.
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EXSTOR - 1 XRS10L240
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FIGURE 1. SYSTEM BLOCK DIAGRAM FOR XRS10L240 IN A DRIVE ENCLOSURE APPLICATION
HA B
D rive E nclosure
ST HD AA D
ST HD AA D ST HD AA D
P ort P ort ultiplier S elector M
HA B
ST HD AA D
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EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR FIGURE 2. PINOUT OF THE XRS10L240
RESETB DRACT0 DRACT1 DRACT2 DRACT3 VSS SOTN0 SOTP0 VDD SORN0 SORP0 VSS VSSA VDDA VSS SORP1 SORN1 VDD SOTP1 SOTN1 VSS VDD VSS PWRDNB ANTEST
REV. 1.05
TRST PORTSEL MDC VSS MDIO VSS SOTN2 SOTP2 VDD SORN2 SORP2 VSS VSSA VDDA VSS SORP3 SORN3 VDD SOTP3 SOTN3 VSS VSS VDD CLKSTN CLKSTP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
HBACT PS_ SIDEBAND _B VSS VDD VSS SiTN1 SiTP1 VDD SiRN1 SiRP1 VSS VDDA VSSA VSS SiRP0 SiRN0 VDD SiTP0 SiTN0 VSS TCK TMS VDD TDO TDI
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
XRS10L 240
VDDA RBIAS VSSA CMU_REFN CMU_REFP VDDA XOG XOD VSSA SCANMODE NC NC VDD NC NC VSS VDDA VSSA VSS NC NC VDD NC NC VSS
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2.0 PIN DESCRIPTIONS TABLE 1: XRS10L240 PIN DESCRIPTIONS
Pin Name Pin Number I/O DATA INTERFACE SOTP0/SOTN0 SOTP1/SOTN1 SOTP2/SOTN2 SOTP3/SOTN3 SORP0/SORN0 SORP1/SORN1 SORP2/SORN2 SORP3/SORN3 SITP0/SITN0 SITP1/SITN1 SIRP0/SIRN0 SIRP1/SIRN1 68, 69 57, 56 8, 7 19, 20 65, 66 60, 59 11, 10 16, 17 93, 94 82, 81 90, 91 85, 84 I O Serial ATA Output Transmitters. These ports communicate from the XRS10L240 to upstream hosts. Serial ATA Input Receivers. These ports receive signals from upstream hosts. CLOCK INTERFACE CMU_REFP/ CMU_REFN 46, 47 I CML AC Coupled Analog Analog Reference clock input I Serial ATA Input Receivers. These ports receive signals from downstream devices O CML AC Coupled DESCRIPTION
Serial ATA Output Transmitters. These ports communicate from the XRS10L240 to downstream devices
XOD XOG
43 44
0 I
Crystal oscillator output Crystal oscillator input, 1.26V max
MDIO INTERFACE SIGNALS MDC MDIO 3 5 I I/O LVCMOS LVCMOS MDIO clock input, +3.3V LVCMOS MDIO data port, +3.3V LVCMOS. Open drain
JTAG Interface Signals TCK TDI TDO 96 100 99 I I O LVCMOS JTAG test clock, +3.3V LVCMOS JTAG test data in, +3.3V LVCMOS JTAG test data out, +3.3V LVCMOS. Open drain. If used to daisy chain JTAG devices, pull up externally using 3.3KOhm resistor. JTAG mode select, +3.3V LVCMOS JTAG test reset, +3.3V LVCMOS. Pull low externally using 3.3KOhm resistor for normal operation of the device.
TMS TRST
97 1
I I
GENERAL CONTROL AND CONFIGURATION SIGNALS (CMOS) RBIAS RESETB 49 75 I I Analog LVCMOS Connection point for calibration termination resistor. Active low reset pin, +3.3V LVCMOS.
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EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 1: XRS10L240 PIN DESCRIPTIONS
Pin Name PWRDNB DRACT[3:0] HBACT Pin Number 52 71, 72, 73, 74 76 I/O I O O LVCMOS LVCMOS LVCMOS DESCRIPTION Active low power down signal for chip, +3.3V LVCMOS. Drive activity port for external LED. Active Low, 3.3V LVCMOS, open drain 0 = Host 0 selected (status) 1 = No Host is selected (status) 0-1-0-1 Toggle (with 1 sec stay at each state) indicates Host 1 is selected. 3.3V LVCMOS +3.3V LVCMOS
REV. 1.05
PS_SIDEBAND_ B
77
I
LVCMOS
Please refer to Table 2, "Host Port Selection," on page 7
2 I LVCMOS Port selector external input pin when this mode is set in the register. Low selects host port 0, otherwise port 1. +3.3V LVCMOS
PORTSEL
TEST PIN ANTEST CLKSTN/ CLKSTP 51 24, 25 O O Analog CML AC Coupled Analog test pin Output clock test pin
RESERVED PINS NC SCANMODE 27, 28, 30, 31, 36, 37, 39, 40 41 I LVCMOS No Connect For factory use only. connect to ground.
POWER AND GROUND SIGNALS VDD 9, 18, 23, 29, 38, 54, 58, 67, 79, 83, 92, 98 14, 34, 45, 50, 62, 87 4, 6, 12, 15, 21, 22, 26, 32, 35, 53, 55, 61, 64, 70, 78, 80, 86, 89, 95 13, 33, 42, 48, 63, 88 I 1.2V supply.
VDDA VSS
I I
1.2V Analog supply. Ground.
VSSA
I
Analog Ground.
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SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 2: HOST PORT SELECTION
HARDWARE PINS REGISTER SETTINGS - REGISTER 0.009A
P_SEL_MTHD P_SIDE_MTHD P_HOST_SEL
COMMENTS
PS_SIDEBAND_ B PIN 77 0
PORTSEL PIN 2 "Selects host port 0 = Host port 0 1 = Host port 1 "Selects host port 0 = Host port 0 1 = Host port 1 x
BIT 0 x
BIT 1 0
BIT 2 x
3.3V LVCMOS
Host port is selected by hardware PORTSEL pin
x
1
0
x
Host port is selected by hardware PORTSEL pin
0
x
1
"Selects host port 0 = Host port 0 1 = Host port 1 "Selects host port 0 = Host port 0 1 = Host port 1 x
"Host port is selected by register 0x0.009A bit 2
x
x
1
1
"Host port is selected by register 0x0.009A bit 2
1
x
0
x
Host port is selected by protocol based selection
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EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 3.0
REV. 1.05
FUNCTIONAL DESCRIPTION
A top-level view of the XRS10L240 is shown in Figure 3 outlining the interfaces to the device and the required support components. The data path can be seen at the top of the device. This includes the two output transmit and input receive paths at the top left, providing the upstream interface to the host, and the four output transmit and input receive paths at the top right, providing the downstream interface to the target devices. The clocking, control, and configuration interfaces are shown below the dotted line. FIGURE 3. XRS10L240 INTERFACES
Serial ATA Upstream Interface to HBAs
SIT_P/N[1:0] SIR_P/N[1:0]
SOT_P/N[3:0] SOR_P/N[3:0]
Serial ATA Downstream Interface to Devices
DRACT[3:0] HBACT
CMU_REF_P/N
Reference Clock
Control and Status Interface
PS_SIDEBAND_B XOD PORTSEL XOG RESETB PWRDNB TCK TDI MDC TDO MDIO TMS TRST
Crystal Oscillator I/O
Configuration Interface
JTAG Interface
VDDA Calibration Resistor 49.9 0.5%
RBIAS
The XRS10L240 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This common building block provides a uniform implementation with common characteristics and a common register map, but provides a functional implementation of independent PHY blocks. Digital logic implementations of Serial ATA link layer blocks along with port selector and port multiplier logic provide the remainder of the data path within the XRS10L240. In addition, management and control interfaces including an
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MDIO interface for register control, a JTAG interface for boundary scan purposes, and a resistor calibration circuit complete the device. A block diagram of the XRS10L240 is shown in Figure 4. FIGURE 4. XRS10L240 BLOCK DIAGRAM
SATA II LINK LAYER
SATA II 3G PH Y
SOT0 SOR 0
SIR 0 SIT0
SATA II 3G PH Y
SATA II LINK LAYER SATA II LINK LAYER RATE ADJUST FIFO SATA II LINK LAYER PO RT MU LTIPLIER SATA II LINK LAYER
SATA II 3G PH Y
SOT1 SOR 1
SIR 1 SIT1
SATA II 3G PH Y PO RT SELECTOR
SATA II 3G PH Y
SOT2 SOR 2
SATA II 3G PH Y
SOT3 SOR 3
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EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 3.1
REV. 1.05
Out Of Band Feature
Each Serial ATA link provides full support for the three Out Of Band (OOB) signals supported by Serial ATA: COMRESET, COMINIT and COMWAKE. These sequences must be separated by idle periods as shown in Figure 5. The sequences are comprised of 106.7ns bursts of activity that are interleaved with varying length stretches of electrical idle. This alternating sequence must be repeated four times to be recognized. FIGURE 5. COMWAKE AND COMRESET/COMINIT SEQUENCES
106.7ns
COMWAKE 106.7ns
COMRESET COMINIT 320ns
An example OOB sequence and the resulting burst and idle widths are shown in Figure 6. If the sequence of burstWidth and idleWidth counts falls within the range specified in the MDIO registers for four consecutive burst/idle sequences, then the link will assert COMINIT or COMWAKE. This OOB signal will remain asserted for as long as the corresponding sequence on the input pins continues. FIGURE 6. EXAMPLE OOB SEQUENCE
rxdP, rxdN squelchClock burstWidth idleWidth 15 17 15 17 15 17
COMINT = (MaxBurstWidthburstWidthMinBurstWidth) && (MaxInitWidthidleWidthMinInitWidth) COMWAKE = (MaxBurstWidthburstWidthMinBurstWidth) && (MaxWakeWidthidleWidthMinWakeWidth)
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3.2
Power Down Modes
The XRS10L240 features independent support for the 3 power modes, as follows:
* Active: All parts of the link are active. All power-down signals are de-asserted. * Partial: In partial mode, the input and output pipelines are shut down, but the PLL and the OOB generation
circuits are active.
* Slumber: In slumber mode, the PLL is also shut down, saving additional power but adding latency on exit.
The XRS10L240 transceiver components (transmitter, receive CDR, PLL, etc.) can be powered down through MDIO register settings. Please refer to Table 14, "Powerdown Registers (MDIO Devices 1, 2 & 3)," on page 29 Please refer to "XRS10L240/140 Errata Sheet" for details regarding Link Power Management. 3.3
Speed Negotiation
The XRS10L240 will automatically perform speed negotiation with the host and devices in order to verify whether the second generation Serial ATA 3.0 Gbps data rate is available or whether the system will need to fall back upon the first generation Serial ATA 1.5 Gbps data rate. Speed negotiation is performed on an independent basis by each of the dual-channel macros. Speed negotiation is done independently on all host and device ports by default. MDIO configuration can request a common negotiated speed on the host and device ports if such a speed exists. To perform speed negotiation with a downstream device, the XRS10L240 will first perform a COMRESET/COMINIT handshake with the device and then performs a calibrate/ COMWAKE handshake. Following receipt of the device COMWAKE signal, the XRS10L240 will continually send out a D10.2 signal while awaiting receipt of the device ALIGN primitive. Depending on the speed of the ALIGN primitive, the XRS10L240 will be able to determine the PHY generation of the device, and provide the appropriate 1.5 Gbps or 3.0 Gbps ALIGN primitive in return to the device, thus completing speed negotiation. This process is outlined in Figure 7. FIGURE 7. SERIAL ATA SPEED NEGOTIATION
For speed negotiation with an upstream host, after the COMRESET/COMINIT and COMWAKE handshake is complete, the XRS10L240 will initially send out an ALIGN primitive at the 2nd generation 3.0 Gbps data rate. If no confirming 3.0 Gbps ALIGN primitive is received from the host, the XRS10L240 will then step down and attempt negotiation at the lower 1.5 Gbps data rate. 3.4
Port selector Implementation
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EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
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The XRS10L240 provides full support for the Serial ATA II Port Selector specification. A Serial ATA Port Selector is a mechanism that allows two different host ports to connect to the same device in order to create a redundant path to that device. Only one host connection to the device is active at a time. The two host ports are responsible for coordination of access to the XRS10L240 by one of two separate means: protocol-based port selection or sideband port selection. Each method is described in detail in the next two sections. 3.4.1 Protocol Based Port Selection
Protocol-based port selection makes use of a sequence of Serial ATA OOB signals to select the active host port. The port selection signal is based on a pattern of COMRESET OOB signals transmitted from the host to the XRS10L240. The port selection signal is composed of a series of COMRESET signals with the timing from one COMRESET signal to the next as shown in Table 3 and Figure 8. The XRS10L240 selects the port, if inactive, on the de-assertion of COMRESET after receiving two complete back-to-back sequences with this defined inter-burst spacing. This can also be identified as two sequences of two COMRESET intervals comprising a total of five COMRESET bursts with four inter-burst delays. Once a port is designated as active, reception of additional COMRESET signals is propagated directly to the device, even if the COMRESET signals constitute a port selection signal. Note that when protocol based selection mode has been enabled, following the initial hardware reset, a single COMRESET burst will select the active host port. After this initial host port selection, only COMRESET OOB observing the protocol timing given below will change the active host. TABLE 3: PORT SELECTOR SIGNAL INTER-RESET TIMING REQUIREMENTS
NOMINAL T1 T2 2.0 8.0 MIN. 1.6 7.6 MAX 2.4 8.4 UNITS ms ms COMMENTS Inter-reset assertion delay for first event of the selection sequence Inter-reset assertion delay for second event of the selection sequence
FIGURE 8. PORT SELECTION SIGNAL - TRANSMITTED COMRESET SIGNALS
3.4.2
Sideband Based Port Selection
The XRS10L240 also features support for a sideband port selection mechanism. This is implemented using a combination of the MDIO register settings and device pins including PS_SIDEBAND_B and PORTSEL. Refer to Table 2 for a sideband port selection settings. 3.5 Port Multiplier Implementation
The XRS10L240 provides full support for the functionality outlined in the Serial ATA II Port Multiplier specification. This Port Multiplier functionality follows the Port Selector implementation, and only one link can be active at any time.
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A Serial ATA II Port Multiplier is a mechanism for one active host connection to communicate with multiple devices. A Port Multiplier is conceptually a simple multiplexer in which one active host connection is multiplexed to multiple device connections. The XRS10L240 uses four bits, known as the PM Port field in all Serial ATA frame types, to route frames between the selected host and the appropriate device. PM ports 0 through 3 are valid device ports within the 4output XRS10L240, while PM port 15 is designated for communication between the host and the XRS10L240 itself. For host-to-device transactions, the PM Port field is designated by the host in order to specify which device the frame is intended for. For device-to-host transactions, the XRS10L240 fills in the PM Port field with the port address of the device that is transmitting the frame. The PM Port field is defined in the Serial ATA port multiplier specification to be the first 32-bit Dword in the Frame Information Structure (FIS) for all FIS types, as shown in Figure 9. FIGURE 9. PORT SELECTION SIGNAL - TRANSMITTED COMRESET SIGNALS
As defined in Serial ATA1.0 PM Port FIS Type
3.5.1
Transmission from a host to a device
A host indicates the target device for receipt of a transmitted frame by setting the PM Port field in the frame to the device's port address. When an XRS10L240 receives a frame as selected from one of the two available hosts by the port selector, it checks the PM Port field in the frame to determine which port address should be used. If the frame is set for transmission to the control port (15), the XRS10L240 receives the frame and performs the command or operation requested. If the frame is designated for a device port, the XRS10L240 obeys the following procedure: 1. The XRS10L240 first determines if the device port is valid. If the device port is not valid, the XRS10L240 will issue a SYNC primitive to the host and terminate reception of the frame. 2. The XRS10L240 determines if the X bit is set in the device port's PSCR[1] (SError) register. If the X bit is set, the XRS10L240 issues a SYNC primitive to the host and terminates reception of the frame. 3. The XRS10L240 determines if a collision has occurred. A collision occurs when a reception is already in progress from the device that the host wants to transmit to. If a collision has occurred, the XRS10L240 will finish receiving the frame from the host and will then issue an R_ERR primitive to the host as the ending status. The XRS10L240 will then discard the frame, but will not return an R_RDY primitive to the host until the frame from the affected device port has been transmitted to the host, thus indicating to the host when it can retry to send the frame. The transmission from the device will proceed as requested, as the device will always take collision precedence over the host. 4. The XRS10L240 initiates a transfer with the device by issuing an X_RDY primitive to the device. A collision may occur as the XRS10L240 is issuing the X_RDY to the device if the device has started transmitting an X_RDY primitive to the XRS10L240, indicating a decision to start a transmission to the host. In this case, the XRS10L240 will finish receiving the frame from the host and then issue an R_ERR primitive to the host to indicate an unsuccessful transmission. The transmission from the device will proceed as requested, as the device will always take collision precedence over the host. 5. After the device issues an R_RDY primitive to the XRS10L240, the XRS10L240 will transmit the frame from the host to the device. The XRS10L240 will not send an R_OK status primitive to the host until the device has issued an R_OK primitive to indicate successful frame reception. In this way, the R_OK status handshake is interlocked from the device to the host. If an error is detected during any part of the frame transfer, the XRS10L240 will ensure that the error condition is propagated to the host and the device. If no error occurs during frame transfer, the XRS10L240 will not alter the contents of the frame, or modify the CRC in any way.
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SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 3.5.2 Transmission from a device to a host
REV. 1.05
A device indicates a transmit to a host in the same way as would be done if the host and device were attached directly. This transaction obeys the following procedure: 1. After receiving an X_RDY primitive from the device, the XRS10L240 will determine if the X bit is set in the device port's PSCR[1] (SError) register. The XRS10L240 will not issue an R_RDY primitive to the device until this bit is cleared to zero. 2. The XRS10L240 will then receive the frame from the device. The XRS10L240 will fill in the PM Port field with the port address of the transmitting device. The XRS10L240 will then check the CRC received from the device, and if valid, it will recalculate the CRC based upon the new PM Port field. If the CRC calculated from the device is incorrect, the XRS10L240 will corrupt the CRC sent to the host to ensure propagation of the error condition 3. The XRS10L240 will issue an X_RDY primitive to the host to start the transmission of the frame to the host. After the host issues an R_RDY primitive to the XRS10L240, the frame from the device, with the updated CRC, will then be transmitted to the host. The XRS10L240 will not send an R_OK status primitive to the device until the host has issued an R_OK primitive to indicate successful frame reception. In this way, the R_OK status handshake will be interlocked from the device to the host. If an error is detected during any part of the frame transfer, the XRS10L240 will ensure that the error condition is propagated to the host and the device.
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3.6
Clocking
The XRS10L240 allows the use of either an external reference clock or of a low cost crystal oscillator to act as a reference clock. Separate device inputs are available for each approach, with full rate reference clock inputs provided on pins CMU_REFP and CMU_REFN, and crystal oscillator inputs provided on pins XOD and XOG. Supported data rates and their appropriate PLL divide factors are outlined in Table 4. TABLE 4: PLL DIVIDE FACTORS
MODE SATA Gen. 2 SATA Gen. 2 SATA Gen. 2 SATA Gen. 2 SATA Gen. 2 SYSCLK 25MHz 50MHz 75MHz 100MHz 150MHz /REF 1 1 1 2 1 /FB 60 30 20 30 10 DINCLK RXCLK 300MHz 300MHz 300MHz 300MHz 300MHz SERIAL CLOCK 1.5GHz 1.5GHz 1.5GHz 1.5GHz 1.5GHz DATA RATE 3.0Gbps 3.0Gbps 3.0Gbps 3.0Gbps 3.0Gbps
NOTE: * All link start with 3.0Gbps, then negotiate down to 1.5Gbps for SATA Generation 1 devices.
3.6.1
Spread Spectrum Clocking
The XRS10L240 provides full support for receipt and generation of signals that have been configured for Spread Spectrum Clocking (SSC) support. The spread technique is implemented by down-spreading the data rate by 0.5% as a means of reducing EMI. Generation of the down-spread clock is performed within the XRS10L240. An example of the resultant spectral fundamental frequency before and after SSC can be seen in Figure 10. FIGURE 10. SPREAD SPECTRUM CLOCKING
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ELECTRICAL SPECIFICATIONS
Serial ATA Specifications
This section contains the electrical specifications for the XRS10L240. 4.1
The XRS10L240 electrical transmit and receive specifications are outlined in this section. The XRS10L240 is fully compliant to the Serial ATA II specification for Gen2i, Gen2x, Gen2m, Gen1i, Gen1x and Gen1m variations at 3.0 and 1.5 Gbps. 4.1.1 Serial ATA Transmitter
A simplified version of the output circuit and test fixture for each of the 6 Serial ATA transmit output pairs on the XRS10L240 is shown in Figure 11. The output differential pair is terminated to the supply VDD. The circuit is designed to be AC coupled. FIGURE 11. SERIAL ATA EQUIVALENT OUTPUT CIRCUIT
The XRS10L240 Serial ATA outputs include a simple one-tap equalizer, that is useful in driving longer printed circuit traces and is a required component in second generation Serial ATA PHYs. This equalizer preemphasizes the output signal whenever there is a data transition. The amount of pre-emphasis can vary between 0 and 45.5%, and is configured via MDIO register settings. Note that pre-emphasis doesn't increase the overall swing, but instead reduces the output amplitude when there is no transition.
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FIGURE 12. EFFECTS OF TRANSMIT PRE-EMPHASIS
The overall swing level can also be modified via MDIO register settings. The XRS10L240 transmit mask is shown in Figure 13. FIGURE 13. TRANSMIT EYE MASK FOR SERIAL ATA OUTPUT
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REV. 1.05
An equivalent circuit for the XRS10L240 Serial ATA inputs is shown in Figure 14. The device receiver mask is shown in Figure 15. This circuit is designed to be AC coupled. The termination resistors are not connected during power-up FIGURE 14. SERIAL ATA EQUIVALENT INPUT CIRCUIT
FIGURE 15. RECEIVE EYE MASK FOR SERIAL ATA INPUT
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SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 5: SERIAL ATA LINK SPECIFICATIONS
NAME tBIT,XS JXR1 JXR1,DJ JXT1 JXT1,DJ tR/tF tQR/tQF tTOL,RX1 VIN VSW2 VIN,IDLE RIN,DIFF RIN,CM3 RIN,OFF RIN,XS S11,IN,DIFF S11,IN,CM Bit Time
DESCRIPTION
MIN. 670 0.32 0.18 0.2 0.2 -5350 175 800 65 85 40 200 40 12 6 12 6 1.5 1.5 0 10 4 4 -
NOM 0 120 100 50 50 -
MAX 333 0.15 0.07 0.46 0.41 350 1600 1200 155 115 60 60 2 0.5
UNITS ps UI UI UI UI UI UI ppm mV mV mV k dB dB dB dB ns ns ns ns ns ns ns
Input Jitter Tolerance Mask at signal crossover Deterministic jitter tolerance at signal crossover Output jitter mask at signal crossover Deterministic output jitter at signal crossover Input signal rise/fall times (20% - 80%) Output signal rise/fall times (20% - 80%) RX to sysclock frequency offset tolerance Input swing, differential peak-peak Output swing, differential peak-peak No swing detection threshold Differential mode input resistance Common mode input resistance Common mode input resistance, no power Output termination resistance Differential input return loss, 50MHz - 1.5GHz Common mode input return loss 50MHz-1.5GHz
S22,OUT,DIFF Differential output return loss 50MHz-1.5GHz S22,OUT,CM tS,REG tH,REG tQ,REG tCYC,REG tHI,REG tLO,REG tRF,REG NOTES: 1. 2. 3. Common mode output return loss 50MHz-1.5GHz Setup time for register port Hold time for register port Clock to Q time for register port Register port clock cycle time R register port clock high time Register port clock low time Register port input rise/fall time
This value includes 0.5% downspread Spread Spectrum clocking, plus 350ppm tolerance around the center frequency. This is measured at the package ball and does not include any board or connector loss. This value can be as low as 5 during power on.
19
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 4.2 CMOS Interface
REV. 1.05
AC and DC specifications for the CMOS inputs and outputs are listed in Table 6. Since all these signals are asynchronous, there are no setup or hold times defined. The CMOS pins are defined in the General Control and Configuration portion of Table 1 in Section 3, "Pin Descriptions". TABLE 6: CMOS I/O SPECIFICATIONS
NAME tDR/tDF,CMOS DESCRIPTION CMOS input signal rise/fall times (20% - 80%) MIN 0.2 0.2 -0.3 1.7 -0.3 2.3 10 -10 NOM 0 3.3 0 MAX 5 5 0.8 3.6 0.4 3.6 20 10 8 5 150 UNITS ns ns V V V V mA mA/ns nH pF uA
tQR/tQF,CMOS1 CMOS output signal rise/fall times (20% - 80%) VIL,CMOS VIH,CMOS VOL,CMOS VPULLUP IOL,CMOS dIOL/dt,CMOS LI,CMOS CI,CMOS ILEAKAGE2 CMOS input low voltage CMOS input high voltage CMOS output low voltage Open Drain Pull-up Voltage Output current for VOL = 0.4V Output current rate of change CMOS I/O inductance CMOS I/O capacitance CMOS I/O Leakage Current
NOTE: .1. This value is measured driving a load of 20pF. NOTE: .2. This values is measured at 2.5 VDC.
4.3
MDIO Interface
The Management Data Input/Output (MDIO) port complies with Clause 45 of the IEEE 802.3ae specification. A representative MDIO driver/receiver is shown in Figure 16. MDIO uses an open drain driver with a pull-up resistor.
20
EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
FIGURE 16. REPRESENTATIVE MDIO CIRCUIT
2.5V/3.3V
Pin To other MDIO Devices
Open Drain Driver
Representative MDIO Read and Write waveforms are shown in Figure 17. The XRS10L240 samples MDIO on the rising edge of MDC for input and drives MDIO after the rising edge of MDC for output. Note that setup, hold, and output timings are defined from the maximum vIL and minimum VIH levels. FIGURE 17. MDIO INPUT AND OUTPUT WAVEFORMS
Values for MDIO parameters are shown in Table 7
21
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
REV. 1.05
TABLE 7: MDIO DC AND AC CHARACTERISTICS
NAME tCYCLE,MDIO tLOW,MDC tHIGH,MDC tS,MDIO1 tH,MDIO2 tQ,MDIO3 tDR/tDF,MDIO tQR/tQF,MDIO4 VIL,MDIO VIH,MDIO VOL,MDIO4 VPULLUP IOL,MDIO dIOL/dt,MDIO LI,MDIO CI,MDIO NOTES: 1. 2. 3. Measured from minimum MDIO VIH to maximum MDC VIL for MDIO rising edge. Measured from maximum MDIO VIL to maximum MDC VIL for MDIO falling edge. Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge. Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge. Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge and MDC rising edge. Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge and MDC rising edge. Measured from maximum MDC VIL to maximum MDIO VIL for MDIO rising edge and MDC falling edge. Measured from maximum MDC VIL to minimum MDIO VIH for MDIO falling edge and MDC falling edge. Measured driving a load of 470pF. DESCRIPTION MDC cycle time MDC low time MDC high time MDIO input to MDC setup time MDC to MDIO input hold time MDC to MDIO output time MDIO input signal rise/fall times (20% - 80%) MDIO output signal rise/fall times (20% - 80%) MDIO input low voltage MDIO input high voltage MDIO output low voltage Open Drain Pull-up Voltage MDIO Output current for VOL = 0.4V MDIO Output current rate of change MDIO input inductance MDIO input capacitance MIN 400 160 160 10 10 0 0.2 0.2 -0.3 1.7 -0.3 2.3 10 -10 NOM 0 3.3 0 MAX 150 100 80 0.8 3.6 0.4 3.6 20 10 8 5 UNITS ns ns ns ns ns ns ns ns V V V V mA mA/ns nH pF
4.
TABLE 8: OPERATING CONDITIONS
Name TA VDD IDD Description Ambient temperature under bias Core power supply voltage Core power supply current Min -40 1.14 Nom 25 1.2 460 Max 85 1.26 600 Units C V mA
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EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 8: OPERATING CONDITIONS
Name VESD1
Description Electrostatic discharge tolerance, Human Body Model Any pin with respect to any other pin except VDDA pins (pins 14, 34, 45, 50, 62, and 87) Electrostatic discharge tolerance, Human Body Model Any pin with respect to VDDA pins (pins 14, 34, 45, 50, 62, and 87) Junction-to-ambient thermal resistance
Min -2000
Nom
Max 2000
Units V
VESD2
-500
500
V
JA
38.5
0
C/W
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EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 5.0 REGISTERS DESCRIPTION The XRS10L240 provides a variety of registers for the purpose of device configuration, testing and monitoring. These registers are accessed through the MDIO interface, outlined in "Section 4.3, MDIO Interface" on page 20. Operational registers available to the customer are given below. Note that all other address space should be left unmodified in order to ensure proper behavior of the device. 5.1 Register Overview
REV. 1.05
The XRS10L240 port address is hardwired to 0; this field should be set to 0 in all packets.The XRS10L240 contains three identical instantiations of a dual Serial ATA PHY macro. A common set of registers exists within each of these macros, and are outlined in "Section 5.2, Macro Registers" on page 25. MDIO device designations 1-3 are used for each of these three macros as shown in Table 9. Registers relating to the XRS10L240 as a whole are outlined in "Section 5.3, XRS10L240 Device Generic Registers" on page 30 and make use of MDIO device 0. TABLE 9: MDIO DEVICE DESIGNATIONS
MDIO DEVICE DESIGNATION 0 1 2 3 MACRO XRS10L240 Device Generic Registers Serial ATA Input Macro Serial ATA Output Macro 0 Serial ATA Output Macro 1 RELEVANT PINS N/A SI0, SI1 SO0, SO1 SO2, SO3
The XRS10L240 registers are arranged as 8-bit fields with 8-bit addresses. These are mapped into the 16-bit MDIO address and data fields by setting the most significant byte of each to 0x00. An example mapping from a macro address/data combination to an MDIO address & data combination is shown in Table 10. TABLE 10: MDIO ADDRESSING
MACRO ADDRESS 0x40 MACRO DATA abcde MDIO ADDRESS 0x0040 MDIO DATA 00000000000abcde
NOTE: The unused upper 3 bits in FBDIV are also set to 0 during MDIO writes and are undefined during MDIO reads.
In the description of each register field, there is an entry describing its read/write status. This may fall into one of the following categories:
* RW- register field is read/write * RO - register field is read only * LL - Latching Low - Used with bits that monitor some state internal to the XRS10L240. When the condition
for the bit to go low is reached, the bit stays low until the next time it is read. Once it is read, its value reverts to the cur-rent state of the condition it monitors.
* LH - Latching High - When the condition for the bit to go high is reached, the bit stays high until the next time
it is read. Once it is read, its value reverts to the current state of the condition it monitors.
* SC - When an SC bit is set, some action is initiated; once the action is complete, the bit is cleared.
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EXSTOR - 1 XRS10L240
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SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
5.2
Macro Registers
The registers outlined in this section are common to each of the three Serial ATA dual PHY macros as described in the previous section. As such, each listed register is present in each of the 1, 2, and 3 MDIO register spaces, and will perform the stated function on the specified Serial ATA lane. The registers within each dual PHY macro are split into the following sections:
Transmit/Receive lane 0 registers: Transmit/Receive lane 1 registers: PLL registers: Bias generator registers: Address range 000***** Address range 001***** Address range 010***** Address range 011*****
TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3)
ADDRESS HEX N.0000 N.0020 BIT(S) 7 6 NAME Reserved SATAPCIEXB_G1 RW RW RW DEFAULT 0 0 DO NOT MODIFY Tx output swing booster bit (Gen 1) 0 = boost swing by 15% 1 = nominal swing DO NOT MODIFY Tx output swing booster bit (Gen 2) 0 = boost swing by 15% 1 = nominal swing DO NOT MODIFY Transmit preemphasis control 000 = 0% transmit preemphasis 001 = 6.5% transmit preemphasis 010 = 13% transmit preemphasis 011 = 19.5% transmit preemphasis 100 = 26% transmit preemphasis 101 = 32.5% transmit preemphasis 110 = 39% transmit preemphasis 111 = 45.5% transmit preemphasis DESCRPTION
5:1 0
Reserved SATAPCIEXB_G2
RW RW
0001 0
N.0001 N.0021
7:3 2:0
Reserved Transmit_Eq0[2:0] Transmit_Eq1[2:0]
RW RW
00000 011
25
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3)
ADDRESS HEX N.0002 N.0022 BIT(S) 7:6 7:6 5:3 5:3 NAME mscProg0[1:0] mscProg1[1:0] Beacon_Swing0[2:0] Beacon_Swing1[2:0] RW RW DEFAULT 10 DESCRPTION Receive equalization control - boost at 1.5GHz *(Note mscProg = '10' default for device Revision E, mscProg = '01' default for device Revision D) Transmit swing size for OOB Signals 000 = 800mV 001 = 700mV 010 = 600mV 011 = 500mV 100 = 400mV 101 = 300mV 110 = 200mV 111 = 0mV Transmit swing size in normal operation 000 = 800mV 001 = 700mV 010 = 600mV 011 = 500mV 100 = 400mV 101 = 300mV 110 =200mV 111 = 0mV Enable receive equalization 0 = enable equalization 1 = disable equalization
REV. 1.05
RW
100
2:0 2:0
Output_Swing0[2:0] Output_Swing1[2:0]
RW
100
N.0003 N.0023
7
enEqB
RW
0
6:0 N.0015 N.0035 7 6:4
Reserved:0] Reserved sysclk25divsel0[2:0] sysclk25divsel1[2:0]
RW RO RW
0010000 DO NOT MODIFY 000 Reserved Divider selection for sysclk-> sysclk25 000 = divide by 1 (sysclk is 25MHz) 001 = divide by 2 (sysclk is 50MHz) 010 = divide by 3 (sysclk is 75MHz) 011 = divide by 4 (sysclk is 100MHz) 100 = divide by 5 (sysclk is 125MHz) 101 = divide by 6 (sysclk is 150MHz) 110 = divide by 10 (sysclk is 250MHz) 111 = divide by 12 (sysclk is 300MHz) DO NOT MODIFY
3:0
Reserved
RW
0101
26
EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3)
ADDRESS HEX N.0018 N.0038
BIT(S) 7:3 2:0
NAME Reserved txbiasbuffsela0[2:0] txbiasbuffsela1[2:0]
RW RW RW
DEFAULT 00100 100 DO NOT MODIFY
DESCRPTION
Tx Predriver swing size in normal operation 000 = 800mV 001 = 700mV 010 = 600mV 011 = 500mV 100 = 400mV (sata default) 101 = 300mV
27
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 12: PLL CONFIGURATION (MDIO DEVICE 1, 2, 3)
ADDRESS HEX N.0040 BIT(S) 7:6 5:0 NAME Reserved FBDIV[5:0] TYPE RO RW DEFAULT 101101 Reserved Divide value for feedback clock 110000 = divide by 5 100000 = divide by 10 100001 = divide by 15 100010 = divide by 20 100011 = divide by 25 100101 = divide by 30 100111 = divide by 50 101101 = divide by 60 (default for 25MHz Ref)) Other - reserved Reserved Divide values for system clock 010000 = divide by 1 (default for 25MHz Ref)) 000000 = divide by 2 000001 = divide by 3 000010 = divide by 4 000011 = divide by 5 000101 = divide by 6 000110 = divide by 8 000111 = divide by 10 001101 = divide by 12 001110 = divide by 16 001111 = divide by 20 Others - reserved Reserved Maximum value for spread (set to 45, [0x2D] when SSCBypass is set to "0") Reserved Selects position of spreading interpolator 0 = Interpolator in feedback path 1 = Interpolator in feedforward path Set to '1' when SSCBypass = '0' DO NOT MODIFY Spread up instead of down DO NOT MODIFY Bypass the saw generator and pulse density modulator and get increment from SSCMax (set SSCMax to 45, 0x2D when SSCBypass is set to 0) DESCRIPTION
REV. 1.05
N.0041
7:6 5:0
Reserved REFDIV[5:0]
RO RW
010000
N.0044
7:6 5:0
Reserved SSCMax Reserved SSCmode
RO RW RO RW
00000 0
N.0045 NOTE 1
7:5 4
3 2 1 0
Reserved SSCInvert Reserved SSCBypass
RW RW RW RW
0 0 0 1
NOTE: 1) In order to enable SSC generation, set register N.0044 to 0x2D, N.0045 to 0x14 and then reset the PLL by writing register 0.0004 to 0x0 then 0xF.
28
EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 13: BIAS GENERATOR CONFIGURATION (MDIO DEVICE 1, 2, 3)
ADDRESS HEX N.0064
BIT(S) 7:4
NAME pr100Tx[3:0]
TYPE RW
RESET VALUE 0x0
DESCRIPTION Transmit pre-driver current bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA DO NOT MODIFY DO NOT MODIFY Transmit driver current bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA
3:0 N.0065 7:4 3:0
Reserved[3:0] Reserved prcal100Tx[3:0]
RW RW RW
0x0 0x0 0x0
TABLE 14: POWERDOWN REGISTERS (MDIO DEVICES 1, 2 & 3)
ADDRESS HEX 1.0080 2.0080 3.0080 BIT(S) 7:6 NAME SIpwrdnDetB[1:0] SO01pwrdnDetB[1:0] SO23pwrdnDetB[1:0] SIpwrdnRxB[1:0] SO01pwrdnRxB[1:0] SO23pwrdnRxB[1:0] SIpwrdnTxDrvB[1:0] SO01pwrdnTxDrvB[1:0] SO23pwrdnTxDrvB[1:0] SIpwrdnTxB[1:0] SO01pwrdnTxB[1:0] SO23pwrdnTxB[1:0] TYPE RW RESET VALUE 11 DESCRIPTION Powers down the signal detector and COM* circuits 1 = normal operation 0 = power down Powers down the receivers and CDR 1 = normal operation 0 = power down Powers down the transmitter 1 = normal operation 0 = power down Powers down the transmit pipes and clock 1 = normal operation 0 = power down
5:4
RW
11
3:2
RW
11
1:0
RW
11
29
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 14: POWERDOWN REGISTERS (MDIO DEVICES 1, 2 & 3)
ADDRESS HEX 1.0081 2.0081 3.0081 BIT(S) 7:2 1 NAME Reserved SIpwrdnBiasGen SO01pwrdnBiasGen SO23pwrdnBiasGen SIpwrdnPLLB SO01pwrdnPLLB SO23pwrdnPLLB TYPE RO RW RESET VALUE 0 Reserved Powers down the bandgap. 1 = power down 0 = normal operation Powers down the PLL 1 = normal operation 0 = power down DESCRIPTION
REV. 1.05
0
RW
1
5.3
XRS10L240 Device Generic Registers
This section outlines generic registers relating to the XRS10L240 as a whole. These registers are accessed through MDIO device 0. TABLE 15: RESET CONTROL SIGNALS
ADDRESS HEX 0.0030 0.0031 0.0032 BIT(S) 7:0 7:0 7:0 NAME revision_id[7:0] device_id [15:8] device_id [7:0 TYPE R/O R/O R/O RESET VALUE 05H 83H 06H DESCRIPTION *(Note 1) Device Revision ID Device ID MSB Device ID LSB
NOTE: 1) Revision ID 05H is for device Revision E. Revision ID 03H is for device Revision D.
TABLE 16: SATA PORT SELECTOR REGISTERS
ADDRESS HEX 0.009A BIT(S) 7:3 2 NAME Reserved p_host_sel TYPE RW RW RESET VALUE 00100 0 DESCRIPTION DO NOT MODIFY Side band port selection 1 = Select Host port 1 0 = Select Host port 0 1 = p_host_sel based sideband selection 0 = external pin based sideband selection
1
p_side_mthd
RW
0
0
p_sel_mthd
RW
0
Please refer to Table 2, "Host Port Selection," on page 7
30
EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 17: CLOCK CONFIGURATION REGISTER
ADDRESS HEX 0.0001
BIT(S) 7:3 2
NAME Reserved refClkSel
TYPE RO RW
RESET VALUE 0 Reserved
DESCRIPTION
1 = select CMU_REF 0 = select on chip crystal oscillator Powers down reference clock Reserved
1 0
pwrdnRefClk Reserved
RW RO
0 -
TABLE 18: PORT MULTIPLIER SATA STANDARD REGISTERS
REGISTER GSCR(0) Product Identifier GSCR(1) Revision Information BIT(S) 31 - 16 15 - 0 31 - 16 15 - 8 7:4 3 2 1 0 GSCR(2) Port Information 7:4 3-0 NAME Device ID Vendor ID Reserved REV_LEV Reserved PM_1,2 PM_1.1 PM_1.0 Reserved Reserved DEV_FAN_OUT_ PORTS TYPE R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O DEFAULT VALUE 0x8306 0x13A8 0x0000 0x03 0x0 1 1 1 0 0x0 0x4 DESCRIPTION Device ID allocated by the vendor. Vendor ID allocated by the PCI-SIG of the vendor that produced the Port Multiplier. 31-16 Reserved 15-8 Revision level of the Port Multiplier. 7-4 Reserved 1=Supports Port Multiplier specification 1.2. 1=Supports Port Multiplier specification 1.1. 1=Supports Port Multiplier specification 1.0. Reserved Reserved Number of exposed device fan-out ports.
31
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
REV. 1.05
TABLE 18: PORT MULTIPLIER SATA STANDARD REGISTERS
REGISTER GSCR(32) Error Information BIT(S) 31 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GSCR(33) Error Information Bit Enable GSCR(64) Port Multiplier Revision 1.X Features Support 31 - 0 NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OR_PORT-3 OR_PORT-2 OR_PORT-1 OR_PORT-0 ERR_INFO_EN TYPE R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O R/O DEFAULT VALUE 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x400FFFF
DESCRIPTION
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused OR of selectable bits in Port 3 PSCR[1] (SError) OR of selectable bits in Port 2 PSCR[1] (SError) OR of selectable bits in Port 1 PSCR[1] (SError) OR of selectable bits in Port 0 PSCR[1] (SError) If set, bit is enabled for use in GSCR[32]
31 - 5 4 3 2 1 0
Reserved PHY_EVENT ASYNC SSC PMREQP BIST Reserved ASYNC_EN SSC_EN PMREQP_EN BIST_EN
R/O R/O R/O R/O R/O R/O R/O RW RW RW RW
0x0 0 1 0 1 0 0x0 0 0 0 0
Reserved 1 = Supports Phy event counters 1 = Supports asynchronous notification 1 = Supports dynamic SSC transmit enable 1 = Supports issuing PMREQP to host 1 = Supports BIST Reserved 1 = Asynchronous notification enabled 1 = Dynamic SSC transmit is enabled 1 = Issuing PMREQP to host is enabled 1 = BIST support is enabled
GSCR(96) Port Multiplier Revision 1.X Features Enable
31 - 4 3 2 1 0
32
EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR TABLE 19: SATA STANDARD REGISTERS - DEVICE PORT (0 TO 3) - STATUS AND CONTROL
NOTE: Registers designated as WC are write clear. In order to clear a particular bit or bit field within a WC designated register, write a `1' to that bit or bit field. REGISTER PSCR(0) (SStatus) BIT(S) 31 - 12 11 - 8 NAME Reserved IPM TYPE R/O R/O DEFAULT VALUE 0x0 0x0 Reserved The IPM value indicates the current interface power management state 0000b = Device not present or communication not established 0001b = Interface in active state 0010b= Interface in Partial power management state 0110b = Interface in Slumber power management state All other values reserved The SPD value indicates the negotiated interface communication speed established 0000b = No negotiated speed (device not present or communication not established) 0001b = Generation 1 communication rate negotiated 0010b = Generation 2 communication rate negotiated All other values reserved The DET value indicates the interface device detection and Phy state. 0000b = No device detected and Phy communication not established 0001b = Device presence detected but Phy communication not established 0011b = Device presence detected and Phy communication established 0100b = Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved See description below See description below DESCRIPTION
7 -4
SPD
R/O
0x0
3-0
DET
R/O
0x0
PSCR(1) (SError) PSCR(2) (SControl)
31 - 16 15 - 0 31 - 19 20 - 16 15 - 12 11 - 8 7-4 3-0
DIAG ERR Reserved Reserved SPM IPM SPD DET
RWC RWC R/O RW RW RW RW RW
0x40 0x0 0x0 0x0 0x0 0x0 0x0 0x4
Reserved All reserved fields shall be cleared to zero. Reserved All reserved fields shall be cleared to zero
See description below See description below See description below See description below
33
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR SError register SCR(1) The Serial ATA interface Error register - SError - is a 32-bit register that conveys supplemental Interface error information to complement the error information available in the Shadow Register Block Error register. The register represents all the detected errors accumulated since the last time the SError register was cleared (whether recovered by the interface of not). Set bits in the error register are explicitly cleared by a write operation to the SError register, or a reset operation. The value written to clear set error bits shall have 1's encoded in the bit positions corresponding to the bits that are to be cleared. Host software should clear the Interface SError register at appropriate checkpoints in order to best isolate error conditions and the commands they impact. Bits [31:16] DIAG The DIAG field contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. The field is bit significant as defined in the following figure.
REV. 1.05
DIAG
R
R
R
R
A
X
F
T
S
H
C
D
B
W
I
N
A Port Selector presence detected: This bit is set to one when COMWAKE is received while the host is in state HP2: HR_AwaitCOMINIT. On power-up reset this bit is cleared to zero. The bit is cleared to zero when the host writes a one to this bit location. B 10b to 8b Decode error: When set to a one, this bit indicates that one or more 10b to 8b decoding errors occurred since the bit was last cleared to zero. C CRC Error: When set to one, this bit indicates that one or more CRC errors occurred with the Link layer since the bit was last cleared to zero. D Disparity Error: When set to one, this bit indicates that incorrect disparity was detected one or more times since the last time the bit was cleared to zero. F Unrecognized FIS type: When set to one, this bit indicates that since the bit was last cleared one or more FISes were received by the Transport layer with good CRC, but had atype field that was not recognized. I Phy Internal Error: When set to one, this bit indicates that the Phy detected some internal error since the last time this bit was cleared to zero. N PHYRDY change: When set to one, this bit indicates that the PHYRDY signal changed state since the last time this bit was cleared to zero. H Handshake error: When set to one, this bit indicates that one or more R_ERRPhandshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 10b/8b decoding error, or other error condition leading to a negative handshake on a transmitted frame. R Reserved bit for future use: Shall be cleared to zero.
S Link Sequence Error: When set to one, this bit indicates that one or more Link state machine error conditions was encountered since the last time this bit was cleared to zero. The Link layer state machine defines the conditions under which the link layer detects an erroneous transition. T Transport state transition error: When set to one, this bit indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared to zero. W COMWAKE Detected: When set to one this bit indicates that a COMWAKE signal was detected by the Phy since the last time this bit was cleared to zero. X Exchanged: When set to one this bit indicates that device presence has changed since the last time this bit was cleared to zero. The means by which the implementation determines that the device presence has changed is vendor specific. This bit may be set to one anytime a Phy reset initialization sequence occurs as determined by reception of the COMINIT signal whether in response to a new device being inserted, in response to a COMRESET having been issued, or in response to power-up.
34
EXSTOR - 1 XRS10L240
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SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
Bits [15:0] ERR The ERR field contains error information for use by host software in determining the appropriate response to the error condition. The field is bit significant as defined in the following figure.
ERR
R
R
R
R
E
P
C
T
R
R
R
R
R
R
M
I
C Non-recovered persistent communication or data integrity error: A communication error that was not recovered occurred that is expected to be persistent. Since the error condition is expected to be persistent the operation need not be retried by host software. Persistent communications errors may arise from faulty interconnect with the device, from adevice that has been removed or has failed, or a number of other causes. E Internal error: The host bus adapter experienced an internal error that caused the operation to fail and may have put the host bus adapter into an error state. Host software should reset the interface before re-trying the operation. If the condition persists, the host bus adapter may suffer from a design issue rendering it incompatible with the attached device. I Recovered data integrity error: A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. This may arise from a noise burst in the transmission, a voltage supply variation, or from other causes. No action is required by host software since the operation ultimately succeeded, however, host software may elect to track such recovered errors in order to gauge overall communications integrity and potentially step down the negotiated communication speed. M Recovered communications error: Communications between the device and host was temporarily lost but was re-established. This may arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PHYRDYn signal between the Phy and Link layers. No action is required by the host software since the operation ultimately succeeded, however, host software may elect to track such recovered errors in order to gauge overall communications integrity and potentially step down the negotiated communication speed. P Protocol error: A violation of the Serial ATA protocol was detected. This may arise from invalid or poorly formed FISes being received, from invalid state transitions, or from other causes. Host software should reset the interface and retry the corresponding operation. If such an error persists, the attached device may have a design issue rendering it incompatible with the host bus adapter. R Reserved bit for future use: Shall be cleared to zero.
T Non-recovered transient data integrity error: A data integrity error occurred that was not recovered by the interface. Since the error condition is not expected to be persistent the operation should be retried by host software.
SControl register SCR(2) The Serial ATA interface Control register - SControl - is a 32-bit read-write register that provides the interface by which software controls Serial ATA interface capabilities. Writes to the SControl register result in an action being taken by the host adapter or interface. Reads from the register return the last value written to it. Bits [19:16] PMP The Port Multiplier Port (PMP) field represents the 4-bit value to be placed in the PM Port field of all transmitted FISes. This field is `0000' upon power-up. This field is optional and an HBA implementation may choose to ignore this field if the FIS to be transmitted is constructed via an alternative method. Bits [15:12] SPM The Select Power Management (SPM) field is used to select a power management state. Anon-zero value written to this field shall cause the power management state specified to be initiated. A value written to this field is treated as a one-shot. This field shall be read as 0000b.
s
0000b = No power management state transition requested
35
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
s s s s
REV. 1.05
0001b = Transition to the Partial power management state initiated 0010b = Transition to the Slumber power management state initiated 0100b = Transition to the active power management state initiated All other values reserved
Bits [11:8] IPM The IPM field represents the enabled interface power management states that may be invoked via the Serial ATA interface power management capabilities
s s s s s
0000b = No interface power management state restrictions 0001b = Transitions to the Partial power management state disabled 0010b = Transitions to the Slumber power management state disabled 0011b = Transitions to both the Partial and Slumber power management states disabled All other values reserved
Bits [7:4]SPD The SPD field represents the highest allowed communication speed the interface is allowed to negotiate when interface communication speed is established
s s s s
0000b = No speed negotiation restrictions 0001b = Limit speed negotiation to a rate not greater than Gen 1 communication rate 0010b = Limit speed negotiation to a rate not greater than Gen 2 communication rate All other values reserved
Bits [3:0] DET The DET field controls the host adapter device detection and interface initialization.
s s
0000b = No device detection or initialization action requested 0001b = Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications reinitialized. Upon a write to the SControl register that sets the DET field to 0001b, the host interface shall transition to the HP1: HR_Reset state and shall remain in that state until the DET field is set to a value other than 0001b, by a subsequent write to the SControl register. 0100b = Disable the Serial ATA interface and put Phy in offline mode. All other values reserved
s s
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRS10L240IV-F XRS10L240IV PACKAGE TYPE 100 Pin LQFP (Lead Free) 100 Pin LQFP OPERATING TEMPERATURE RANGE -40 to +85 C C -40 to +85 C C
36
EXSTOR - 1 XRS10L240
REV. 1.05
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 100 LEAD LOW-PROFILE QUAD FLAT PACK
(14 X 14 X 1.4 mm LQFP, 1.0 mm FORM)
D D1 75 51
76
50
D1
D
100
26
1
25
A Seating Plane A1 A2
e
B C
L
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2008 EXAR Corporation Datasheet January 2009. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
37
EXSTOR - 1 XRS10L240
SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR
NOTE: The control dimension is in millimeters INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.055 0.002 0.053 0.010 0.004 0.622 0.390 MAX 0.063 0.006 0.057 0.014 0.008 0.638 0.555 MILLIMETERS MIN 1.40 0.05 1.35 0.17 0.09 15.80 13.90 MAX 1.60 0.15 1.45 0.27 0.20 16.20 14.10
REV. 1.05
0.0197 BSC 0.018 0 7 typ 0.030 7
0.50 BSC 0.45 0 7 typ 0.75 7
REVISIONS
REV # 1.00 1.01 1.02 1.03 DATE November 2008 January 2008 March 2008 June 2008 Released. Corrected JTAG TRST, TDO pin desc., part ordering info. Revised to operational registers. Corrected ESD tolerance to 2000V/500V (Table 8) Added more description for "Section 3.2, Power Down Modes" on page 11 - added reference to "XRS10L240/140 errata 1.04 1.05 August 2008 January 2009 Removed references to link power management Chaged register default for Rx Equalization, corrected HBACT pin definition. DESCRIPTION OF CHANGES
38

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